1. Field of the Invention
The present invention generally relates to data communications in a computer system and, more particularly, to memory control design to support synchronous Dynamic Random Access Memory (SyncDRAM) type memory.
2. Description of Related Art
In conventional central processing unit (CPU) designs, speed in which data is transferred within the CPU has been increasing rapidly with the advent Reduced Instruction Set Computers (RISC) architectures and even more so due to extensive use of pipelining. However, unlike the CPU development, development of different types of memory has concentrated on increasing media density in order to reduce the cost per bit of memory and not speed. This disparity has created an imbalance in memory bandwidth required for small low-cost systems. External interleaving to improve memory bandwidth has been employed to overcome this problem, but has failed. External interleaving has become a less favorable option due to use of asynchronous interfaces, high timing margins, high data rate, and a lack of registers for control signals, addresses and input/outputs. The cost of external interleaving is also high due to additional glue logic and total memory density required for a given bandwidth. This imbalance created the need for syncDRAM type memory units.
SyncDRAMs offer extensive memory density with low cost and high bandwidth memory architecture. Furthermore, syncDRAMs are able to support various applications like mainstore, peripherals, graphics and video. SyncDRAMs are designed for a wide range of applications with programmable features such as latency, burst length and burst-type. They can support single or dual bank high frequency and low power operations.
A key feature provided by syncDRAMs is immediate access to multiple blocks of data called "bursts." Burst length refers to the number of words that will be output or input in a read or write cycle respectively. After a read burst has completed, the output bus will become high impedance. The burst length is programmable as 1, 2, 4 or 8 words, or full page. The ability of the CPU to access these bursts of information gives the CPU access to wider bandwidth of memory.
The syncDRAM operates similar to its predecessor DRAM with further advanced features. Unlike conventional DRAMs, the syncDRAM is able to provide bursts of data in a series of 0 to 8 words in a single cycle or, when in page mode, can transfer a burst of an entire page to a destination unit. In a typical sequence, a microprocessor in the computer system will send a read or write request through the system bus to the memory control. The memory control will generate a signal which is sent through the DRAM bus to the syncDRAM for execution. Once the command is received by the syncDRAM, the syncDRAM proceeds with a preprogrammed sequence for transferring the data.
The syncDRAM must be initialized in the power-on sequence, much like conventional DRAMs, before data can be transferred. During initialization, the syncDRAM internal clock and data mask must be activated to avoid having data written into the syncDRAM during the sequence. There is typically a 100 ms delay that proceeds any commands being handled by the syncDRAM after the initiation sequence has begun. When asserting a command, a chip enable must be asserted so that commands are recognized by the syncDRAM for execution. Within the syncDRAM, commands executed correspond to the rising edge of the internal clock. When a command is sent to the syncDRAM, a clock enable signal (CE) allows the syncDRAM to receive the command and determine the validity of the next clock cycle. If the clock enable is high, the next clock rising edge is valid, otherwise it is invalid. If the clock rising edge is invalid, the internal clock is not asserted and operations in the syncDRAM are suspended. In conventional use, each time a command is asserted to the syncDRAM to transfer data, the chip must be initiated using the chip select and the clock enable in the same clock in order for the command to be recognized by the syncDRAM.
Once the chip is initialized with concurrent assertion of the chip enable and clock enable commands, data transfer can begin. When the address is valid, a page hit occurs and the syncDRAM is then ready to transfer data. The page is then indexed for specific data to be transferred. If an address request is invalid, however, a page miss occurs and a new page must then be opened to properly locate the requested data.
According to the preset burst rate, a series of words are then transferred to the syncDRAM unit in response to a write request or from the syncDRAM unit in response to a read request. In the case where data is not ready to be transferred, either in a read or write request, the syncDRAM continues to transfer the burst of data regardless of the data's readiness. In the case of a read request, data is continually read from an initial burst start address once initiated. Following the initial transfer of the word from the burst start address, an internal address incrementer in the syncDRAM increments the reading pointer to transfer consecutive words following the burst start address up to the end of the burst length preset by the DRAM whether the data path controller is ready to accept data or not.
Similarly, during a write sequence, after an initial word is transferred to the burst start address, the internal incrementer then increments the internal address to receive consecutive words following the burst start address in subsequent addresses regardless of whether or not data is ready at the sending device. The data path controller 18 determines whether data will be transferred.
In operation, the syncDRAM can be enabled by a command from a memory control unit responding to a data transfer request from the CPU. The syncDRAM responds with an initiation process that includes internally latching an address from which data will be read or written to. Each time a burst of data is requested, the syncDRAM must go through the initiation sequence in order to access the address from which data will be read or written. The time it takes to complete the initiation process will deficit the overall memory retrieval time needed to access the data.
Accordingly, it would be of great use to a computer industry to further speed up the already efficient syncDRAM memories by reducing the time it takes to access the syncDRAMs by reducing the time it takes to initiate the data retrieving cycle. In the event data is not ready to be transferred, conventional implementations require a second request to send data to or read data from the syncDRAM when the data is ready. This requires a subsequent read or write request which requires initializing the syncDRAM and opening a page again.
The operation of reading from the syncDRAM, in particular, requires not only initiating the syncDram, but also opening a particular page as well as the location on a page where specific data is located. To eliminate one or more of these steps in the reading operation would significantly speed up the reading operation, thus, making data available to the computer system much faster. As will be seen, the present invention in one embodiment, accomplishes this in a simple and elegant matter.